1. Field of the Invention
The present invention relates, for example, to a communication system, receiver and reception method using a low-amplitude data transmission technique capable of providing high-speed data transmission between chips in proximity to each other.
2. Description of the Related Art
In related art, the I/O (input/output) standards commercialized to date for high-speed data transmission between chips in proximity to each other such as SSTL—1.8 and LVDS have the following drawbacks.
Firstly, if the supply voltage was changed or a finer manufacturing process was introduced, it was impossible to establish connection. Therefore, it was necessary to take the trouble of adding a manufacturing step adapted to manufacture an I/O circuit with elements having an obsolete structure, which resulted in reduced performance and increased cost.
Secondly, although the power consumption of the line drivers alone is as much as several tens of W/Ch., the transmission rate is low or 600 Mbps. As a result, it is impossible to deliver data bandwidths of 10 Gbps or more which are considered necessary for future video mobile equipment because of the power consumption and LSI pin count.
In order to solve these problems, a variety of low-amplitude data transmission techniques have been proposed (refer, for example, to Mats Hedberg et al., “I/O Family with 200 mV to 500 mV Supply Voltage,” ISSCC Dig. of Technical Papers pp. 340-341, 1997, R. Palmer et al., “A 14 mW 6.25 Gb/s Transceiver in 90 nm CMOS for Serial Chip-to-Chip Communications”, and USP Publication No. 5761244 (hereinafter referred to as Non-Patent Documents 1 and 2 and Patent Document 1)).
By the way, a low-amplitude data transmission technique adapted to transmit data, for example at an amplitude of 0.2 V, is used for this type of communication system between chips in proximity to each other.
A so-called source synchronous technique is used for such transmission.
In a source synchronous communication method, the transmitter transmits data and a clock synchronous with the data, and the receiver latches the received data in synchronism with the received clock signal.
FIG. 1 is a diagram illustrating a configuration example of a typical communication system using a low-amplitude data transmission technique.
A communication system 1 shown in FIG. 1 includes a transmitter 2, receiver 3 and transmission line 4.
The transmitter 2 includes a data selector 21 and line drivers 22 and 23 and transmits a plurality of transmission data DT1 and STD2 phase-locked to each other and a clock signal CLK, which is synchronous with the transmission data, to the receiver 3 via the transmission line 4.
The receiver 3 includes amplifiers 31 and 32, a digital locked loop (DLL) 33, clock buffer 34 and data reproduction circuit 35. The amplifiers 31 and 32 amplify the low-amplitude data and clock to the amplitude appropriate to the supply voltage of the chip. The digital locked loop 33 generates a reproduction clock RCK phase-locked to the clock signal CLK that has been amplified by the amplifier 31. The data reproduction circuit 35 reproduces the transmitted data DT1 and DT2 amplified by the amplifier 32 in synchronism with the reproduction clock RCK.